Reduced overlap

[PJW]

Hi PJW,

Could you please explain the meaning of Reduced overlap supported with circuits?

Thanks Mr.PJW.

Thought I'd answered this before, but can't find it- think may have lost internet connection to website when posting previously, so apologies for the wait.

A reduced overlap is only an overlap of less than a full overlap length (typically 180m, but to modern standards and particularly when over 100mph 225m) justified by virtue of a risk assessment due to relatively slow approach speed, site conditions etc meaning that likelihood of SPAD and consquences of SPAD are both regarded as acceptable. There are no special circuits. it is provided INSTEAD OF a full overlap.


I expect that you are really thinking of what is nowadays called a restricted overlap - confusingly this was called a reduced overlap in the past (and those of my generation and older always have to do a "double take" to ensure we use the right terminology).
This is provided IN ADDITION TO a full overlap.
At aspect level the circuits are the same except for the fact that a shorter length of overlap applies an d therefore it proves fewer track sections and probably a lower number of points than are within the full overlap. Typically but not always there will be one set of triling points within the full overlap which are excluded from the restricted overlap.
A restricted overlap is associated with a WARNING class route at the signal9s) n rear that read up to the exit signal having the ROL.

The "special circuits" are:
a) the (W) NLR/RLR which are basically similar to the normal (M)NLR/RLR (apart from the smaller extent of what is proved)
b) the (W) NLR/RLR is cross-proved against the (M)NLR/RLR and vice versa
c) various controls which make the (W) step-up to a (M) when the forward route is set, the full overlap aspect conditions are satisfied and the signal itself is not approach locked. Actually this condition is only strictly needed for RRI [to prevent the aspect reverting briefly- since it takes a finite time for the route relays to change state and the cross-proving prevents the (M)NLR being unlatched until the (W)NLR has been latched up again]. In SSI the class of route can be exchanged within the execution of a single instruction which is executed between the output telegram being calculated for the next cycle of the interlocking- the signal remains off as the TFM only gets periodic updating on each major cycle of the SSI and remains displaying an aspect as previously calculated for a duration not exceeding 1 second and hence the reversion prblem would not occur.

I am not sure that providing circuits would actually be very useful to aid understanding- they are obviously site specific and I hope that my explanation above assists. If however you find a diagram more useful than a wordy explanation let me know and I'll try to look out / construct a typical when I have more time